The present invention relates to Very Large Scale Integrated (VLSI) circuit accelerated bus line communication. In particular, the present invention relates to bus amplification circuits.
Highly integrated circuits such as microprocessors, application specific integrated circuits (ASICs) and some memory devices utilize bus lines for the communication of data between at least two points. In memory devices for example, data buses are used to carry data from the memory core to input/output pads. In microprocessors and ASICs, buses are commonly used to carry information to various blocks within the chip. Data buses can be uni-directional, where data is always transmitted in one direction, or bi-directional, where data can be transmitted in either direction. In both types however, the speed at which data is transmitted along the data bus can limit the overall performance of the integrated circuit.
Another type of integrated circuit device that makes use of bus lines is computational random access memory (CRAM). CRAM is a memory device having arrayed parallel processors with hundreds to thousands of processors commonly connected to a shared bus line. CRAM is a processor in memory architecture that takes advantage of the large internal memory bandwidth available at the sense amplifiers. By pitch matching each bit serial processing element (PE) to one or more memory columns, CRAM can operate as a massively parallel single instruction stream, multiple data stream (SIMD) computer. CRAM architectures and arrayed parallel processor architectures are well known in the art.
An example of a prior art CRAM is shown in FIG. 1. The CRAM 20 shown in FIG. 1 includes two banks 22 and 24, labeled xe2x80x9cBank 1xe2x80x9d and xe2x80x9cBank 2xe2x80x9d respectively, although a CRAM can contain any number of banks. Bank 22 includes a memory array 26 coupled to peripheral circuits such as row decoders 28, processing elements (PEs) 30, and column decoders 32. Bank 24 is identically configured to bank 22, and includes a memory array 34 coupled to peripheral circuits such as row decoders 36, PEs 38, and column decoders 40. Memory arrays 26 and 34 can be of any type of memory, such as dynamic random access memory (DRAM) or static random access memory (SRAM), for example, with row decoders 28 and column decoders 32 selecting particular memory cells for read and write operations. Each PE 30 has direct access to a single column of memory for use as its local memory, and is coupled to a common broadcast bus 42. As shown in FIG. 1, PEs 30 and 38 are all coupled to the same broadcast bus 42, which can further extend to other banks of the chip. The PEs 30 are connected to the common broadcast bus 42 in a wired AND configuration, allowing the common broadcast bus 42 to function as a dynamic zero detect circuit. Furthermore, if at least one PE 30 writes a zero to the common broadcast bus 42, all other PEs 30 receive the zero value for register write back.
An example of a prior art PE 30 or 38 used in CRAM 20 of FIG. 1 is shown in FIG. 2. A pair of adjacent PEs 30 are shown in FIG. 2, illustrating the interconnections between each other and the broadcast bus 42. The presently shown PEs 30 support bit-serial computation, left-right nearest-neighbor communication, wired-AND broadcast bus evaluation and external databus access. The data processing components of PEs 30 are not relevant to the present invention and hence not discussed in detail, except for transceivers 50 which are responsible for communicating data between the PE 30 and the broadcast bus 42. The memory can also be accessed externally through a conventional databus 52 connected to sense amplifier circuit 54.
Because the broadcast bus 42 is long, and is capacitively loaded due to the numerous transceivers 50 connected to it, global communication between PEs 30 via the wired AND broadcast bus line is slow. As is known to those of skill in the art, factors that limit bus speed performance are its capacitive load and wiring resistance, both of which increase in proportion to its wiring density and length. The capacitive load of the bus also increases as more transistors, such as transceivers 50, are coupled to it.
Hence, the switching rate and the time to reverse bus line charge are degraded and overall performance is adversely affected. Unfortunately, maximum device performance demands that charge reversal of the bus line be completed within the shortest time possible while taking into account adequate noise margins while ensuring reliable data recognition.
The circuits and techniques proposed in the art for improving bus line performance include mid-point precharge schemes, sensing of small voltage changes, segmenting bus lines, and other various schemes for reducing bus line capacitance or speeding up signal transmission. Unfortunately, many of the proposed solutions are not suitable for bi-directional signal transmission since their circuits require control signals to indicate the direction of the data. This can add design overhead and impose control signal timing constraints.
It is, therefore, desirable to provide a bus amplifier circuit and method for providing high-speed operation of a bi-directional bus line.
It is an object of the present invention to obviate or mitigate at least one disadvantage of previous bi-directional bus line amplifier circuits and methods. In particular, it is an object of the invention to provide a high-speed bi-directional bus line architecture.
In a first aspect, the present invention provides a bi-directional amplifier circuit for driving data between first and second complementary bus lines and third and fourth complementary bus lines. The bi-directional amplifier circuit includes a precharge circuit, a pre-discharge circuit, discharge circuit, and a charge circuit. The precharge circuit charges the first bus line to a high logic level. The pre-discharge circuit discharges the second bus line to a low logic level. The discharge circuit drives the first bus line to the low logic level in response to a change in the logic level of one of the second bus line and the fourth bus line. The charge circuit drives the second bus line to the high logic level in response to a change in the logic level of one of the first bus line and the third bus line.
In an embodiment of the present aspect, an enable signal activates the discharge circuit and disables the pre-discharge circuit, and an inverted enable signal activates the charge circuit and disables the discharge circuit. The precharge circuit includes a p-channel transistor having a gate terminal for receiving the enable signal, and the pre-discharge circuit includes an n-channel transistor having a gate terminal for receiving the inverted enable signal.
According to an aspect of the present embodiment, the discharge circuit includes a first discharge transistor for discharging the first bus line to the low logic level in response to the high logic level of the fourth bus line, and the charge circuit includes a first charge transistor for charging the second bus line to the high logic level in response to the low logic level of the third bus line. In the present aspect, the discharge circuit includes second and third discharge transistors serially connected between the first bus line and VSS, where the second discharge transistor has a gate terminal for receiving the second bus line, and the third discharge transistor has a gate terminal for receiving the enable signal. The charge circuit includes second and third charge transistors serially connected between the second bus line and VDD, where the second charge transistor has a gate terminal for receiving an inverted enable signal, and the third charge transistor has a gate terminal for receiving the first bus line.
In an alternate embodiment of the present aspect, the discharge circuit includes a second discharge transistor connected between the first bus line and the enable signal, and the second discharge transistor has a gate terminal for receiving the second bus line. The charge circuit includes a second charge transistor connected between the second bus line and the inverted enable signal, and the second charge transistor has a gate terminal for receiving the first bus line.
In yet another embodiment of the present aspect, a first keeper transistor has a gate terminal connected to the second bus line for coupling VDD to the first bus line, and a second keeper transistor has a gate terminal connected to the first bus line for coupling the second bus line to VSS.
In another embodiment of the present aspect, multiple discharge and charge circuits are coupled to the first and second bus lines.
In a second aspect, the present invention provides a bi-directional amplifier circuit for driving data between first and second complementary bus lines, and third and fourth complementary bus lines, where the first and third bus lines are precharged to a first predetermined logic level and the second and fourth bus lines are precharged to a second predetermined logic level. The bi-directional amplifier circuit includes a first local bi-directional amplifier circuit coupled to the first and second complementary bus lines for receiving the third and fourth complementary bus lines, and a second local bi-directional amplifier circuit coupled to the third and fourth complementary bus lines for receiving the first and the second bus lines. The first local bi-directional amplifier circuit accelerates charge reversal of the first and second complementary bus lines in response to a change in the logic levels of one of the third and fourth complementary bus lines and the first and second complementary bus lines. The second local bi-directional amplifier circuit accelerates charge reversal of the third and fourth complementary bus lines in response to a change in the logic levels of one of the first and second complementary bus lines and the third and fourth complementary bus lines.
According to an embodiment of the present aspect, the first local bi-directional amplifier circuit includes a precharge circuit, a pre-discharge circuit, a discharge circuit and a charge circuit. The precharge circuit precharges the first bus line to the first predetermined logic level. The pre-discharge circuit precharges the second bus line to the second predetermined logic level. The discharge circuit drives the first bus line to the second predetermined logic level in response to a change in the logic level of one of the second bus line and the fourth bus line. The charge circuit drives the second bus line to the first predetermined logic level in response to a change in the logic level of one of the first bus line and the third bus line.
In an aspect of the present embodiment, the precharge circuit includes a p-channel transistor having a gate terminal for receiving the enable signal, and the pre-discharge circuit includes an n-channel transistor having a gate terminal for receiving an inverted enable signal. The discharge circuit can include a first discharge transistor for discharging the first bus line to the low logic level in response to the high logic level of the fourth bus line. The charge circuit can include a first charge transistor for charging the second bus line to the high logic level in response to the low logic level of the third bus line.
According to another aspect of the present embodiment, the discharge circuit cam include second and third discharge transistors serially connected between the first bus line and VSS. The second discharge transistor has a gate terminal for receiving the second bus line and the third discharge transistor has a gate terminal for receiving the enable signal. The charge circuit includes second and third charge transistors serially connected between the second bus line and VDD. The second charge transistor has a gate terminal for receiving the inverted enable signal, and the third charge transistor has a gate terminal for receiving the first bus line.
In yet another aspect of the present embodiment, a first keeper transistor has a gate terminal connected to the second bus line for coupling VDD to the first bus line, and a second keeper transistor has a gate terminal connected to the first bus line for coupling the second bus line to VSS.
In a third aspect, the present invention provides a method of bi-directionally driving data between first and second complementary bus lines and third and fourth complementary bus lines. The method includes precharging the first and third complementary bus lines to a first predetermined logic level, precharging the second and fourth complementary bus lines to a second predetermined logic level, changing the first precharged bus line to the second predetermined logic level in response to a change in the logic level of one of the second bus line and the fourth bus line, and changing the second precharged bus line to the first predetermined logic level in response to a change in the logic level of one of the first bus line and the third bus line.
In embodiments of the present aspect, the step of precharging includes precharging the first and third bus lines to the high logic level, and pre-discharging the second and fourth bus lines to the low logic level. The step of precharging is initiated by an inactive level of an enable signal. The step of discharging and charging is initiated by an active level of the enable signal.
In a fourth aspect, the present invention provides a computational random access memory having a plurality of memory columns. The computation random access memory includes processing elements, a complementary pair of sub-broadcast bus lines, a complementary pair of short broadcast bus lines, and a bi-directional bus amplifier circuit. The processing elements are associated with the memory columns for executing computational functions. The complementary pair of sub-broadcast bus lines receive input data from processing elements and provide output data to the processing elements. The complementary pair of short broadcast bus lines receive the input data from the complementary pair of sub-broadcast bus lines and provide the output data to the complementary pair of sub-broadcast bus lines. The bi-directional bus amplifier circuit accelerates charge reversal of the complementary pairs of sub-broadcast bus lines and short broadcast bus lines.
In an embodiment of the present aspect, each processing element includes a transceiver circuit for providing the input data to the complementary pair of sub-broadcast bus lines and receiving the output data from the complementary pair of sub-broadcast bus lines. The transceiver circuit can include a receive circuit and a transmit circuit. The receive circuit receives the input data from one sub-broadcast bus line of the complementary pair of sub-broadcast bus lines. The transmit circuit drives the complementary pair of sub-broadcast bus lines with the output data.
In an aspect of the present embodiment, the receive circuit can include a first NAND gate having one input connected to the one sub-broadcast bus line and a second input for receiving an enable signal. The transmit circuit can further include a second NAND gate and a drive circuit. The second NAND gate has one input for receiving the enable signal and a second input for receiving the output data, for providing an activation signal. The drive circuit drives the complementary pair of sub-broadcast bus lines to complementary logic levels corresponding to the output data in response to the activation signal. The drive circuit can further include an, inverter for receiving the activation signal and providing an inverted activation signal, a p-channel transistor for coupling the one sub-broadcast bus line to VDD in response to the activation signal, and an n-channel transistor for coupling the other sub-broadcast bus line to VSS in response to the inverted activation signal.